FIELD OF THE INVENTION
The invention relates to integrated circuit manufacture, in particular to a method of manufacturing a capacitor electrode in an integrated semiconductor circuit.
Integrated semiconductor circuits frequently have capacitors which are raised during the manufacturing process, i.e., they are produced on an approximately horizontal surface. An example of this are so-called stacked capacitor memory cells, in particular in DRAM components. The choice of capacitor dielectric has an important effect on the space requirement of such a capacitor.
Conventional capacitors mostly make use of silicon oxide layers or silicon nitride layers as storage dielectric. Those have a dielectric constant of at most approximately 8. New paraelectric materials such as, for example, BST (barium strontium titanate, BaSrTiO.sub.3) and similar materials, have a dielectric constant .epsilon.&gt;150, and thus render a smaller capacitor possible.
Such memory elements with a paraelectric material as capacitor dielectric (DRAM) lose their charge, and thus their stored information, when the supply voltage fails or is turned off. Furthermore, because of the residual leakage current, conventional memory elements must continuously be rewritten (refresh time). Because of the different polarization directions, the use of a ferroelectric material as storage dielectric permits the construction of a nonvolatile memory, which does not lose its information in the event of failure of the supply voltage, and need not continuously be rewritten. The residual leakage current of the cell does not influence the stored signal. An example of such a ferroelectric material is PZT (lead zirconium titanate, Pb(Zr,Ti)O.sub.3).
The production of these novel ferroelectric materials and paraelectric materials is generally performed at high temperatures in an oxidizing atmosphere. Consequently, there is no need, in particular for the first capacitor electrodes, of materials which are compatible with these conditions. A suitable material for this purpose seems to be an electrode made from platinum. The structuring of platinum, in particular of a relatively thin platinum layer is, however, a largely unsolved problem to date, since no suitable etching process has yet been developed, and since no volatile platinum compounds seem to be suitable for RIE processes. Etching processes to date are based on the application of a resist mask and etching in argon, oxygen or chlorine plasmas. In this case, because of the physical components of the process, only limited selectivity can be achieved with respect to mask materials and substrate.